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It looks at the address I pass to it, then it moves from there to the start of the first cache line and only then begins invalidating the cache. I have tried simply disabling the entire cache at the start of the program, however this doesn't seem to work.

This also includes the lines for the mutex (which is usually implemented as a value in memory).

Of course, there are architecture-specific details, but this is how it works in general.

This leads to varying parts of my packet information being "chopped off". A solution to this, as stated in the Xilinxs documentation seems to be to cache align the... I don't know if it is my attempt that doesn't work, or if it simply doesn't fix the problem.

I've got caching turned on, and it works great, but I want to have a refresh button to reload data retrieved from the server.

I then copy out the packets into some linked list containers that I have before returning the BDs to the hardware.

My problem is that when I go to read the data that the BD points to, the cached data is wrong, so I invalidate it.

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So, in some cases, a solution is possible if there is some other thing that does know about it and can notify us.

In the given example, the get Data function could hook into the file system, which does know about all changes to files, regardless of what process changes the file, and this component in turn could notify the component that transforms the data.

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